CAT28C256G-15T【PDF 9/14 页】IC EEPROM 256KB PARALLEL 32PLCC

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CAT28C256

Hardware Data Protection

The following is a list of hardware data protection features

that are incorporated into the CAT28C256.

1. V CC sense provides for write protection when V CC

falls below 3.5 V min.

2. A power on delay mechanism, t INIT (see AC

characteristics), provides a 5 to 10 ms delay before

a write sequence, after V CC has reached 3.5 V

min.

3. Write inhibit is activated by holding any one of

OE low, CE high or WE high.

4. Noise pulses of less than 20 ns on the WE or CE

inputs will not result in a write cycle.

Software Data Protection

The CAT28C256 features a software controlled data

protection scheme which, once enabled, requires a data

algorithm to be issued to the device before a write can be

performed. The device is shipped from ON Semiconductor

with the software protection NOT ENABLED (the

CAT28C256 is in the standard operating mode).

WRITE DATA:

ADDRESS:

WRITE DATA:

ADDRESS:

WRITE DATA:

ADDRESS:

AA

5555

55

2AAA

A0

5555

WRITE DATA:

ADDRESS:

WRITE DATA:

ADDRESS:

WRITE DATA:

ADDRESS:

AA

5555

55

2AAA

80

5555

SOFTWARE DATA

PROTECTION ACTIVATED (Note 15)

WRITE DATA:

ADDRESS:

AA

5555

WRITE DATA:

XX

WRITE DATA:

55

TO ANY ADDRESS

WRITE LAST BYTE

TO

LAST ADDRESS

ADDRESS:

WRITE DATA:

ADDRESS:

2AAA

20

5555

Figure 10. Write Sequence for Activating

Software Data Protection

Figure 11. Write Sequence for Deactivating

Software Data Protection

15. Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t BLC Max.,

after SDP activation.

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